The present invention generally relates to Josephson integrated circuits having a Josephson processor therein, and more particularly to a Josephson integrated circuit having a construction for facilitating the exchange of data between the Josephson processor and peripheral circuits cooperating therewith with a reduced clock rate.
Intensive efforts are in progress to fabricate Josephson integrated circuits. Therein, the Josephson devices, utilizing the Josephson junction of Nb and the like for logic operation, are assembled to form a digital processor. Such Josephson devices are characterized by extremely high operational speed and low power consumption. Thus, the device is particularly suited for constructing ultra-high speed digital computers and processors.
In such a high speed Josephson digital processor, there arises a problem in that, although the operational speed within the processor is enormously high, the speed of processing in the peripheral processors, usually constructed as conventional silicon or compound semiconductor devices, is not as large or high as in the Josephson processor. It should be noted that the Josephson processors utilize the transition between the superconduction state and the normal conduction state of the Josephson junction for logic operation, and because of this, the Josephson processors should be operated at an extremely low temperature environment. Thus, the fabrication of an entire computer or signal processing system by a single Josephson processor is not realistic.
When conventional semiconductor devices are used for the peripheral circuits, the transfer of data between the Josephson processor and the peripheral semiconductor circuits has to be made with a reduced clock rate. Because of this, there is a need to provide a conversion circuit for converting the data output from the Josephson processor to the peripheral processing circuits without undermining or affecting the high speed processing capability of the Josephson processor.
Conventionally, a conversion circuit shown in FIG. 1 has been known for the above-mentioned purpose. The circuit of FIG. 1 is described by Ohara et al., "JOSEPHSON SERIAL-PARALLEL CONVERTER," Extended Abstracts of 1989 International Superconductivity Electronics Conference (ISEC'89), sponsored by the Japan Society of Applied Physics and held Jun. 12-13, 1989 in Tokyo, which is incorporated herein as a reference.
Referring to FIG. 1, the conversion circuit includes shift registers 1a-1h, 2a-2h, 3a-3h, . . . arranged into a number of columns. Each column of the shift registers are connected to a Josephson processor not illustrated. To avoid the complexity in the drawing, the reference numerals are given to only a part of the shift registers.
In each column of the shift registers, there are provided a plurality of shift registers in correspondence to the number of bits of the output data to be obtained from a single bit output of the Josephson processor. Thus, when converting single bit data produced serially from the Josephson processor into eight bit parallel data in each column, there are provided eight shift registers 1a-1h, 2a-2h, . . . in respective columns. In each column, the shift registers, such as the shift register 1a, have respective branched outputs and there are formed a number of eight bit output channels CH1, CH2, . . . at the bottom level of the shift register column.
In operation, the output data from the Josephson processor is written into the shift registers in each column sequentially. For example, the output data is written into the shift register 1a and transferred sequentially along to the registers 1b, 1c, . . . up to the register 1h. In response to this, there appears eight bit parallel data CH1 DATA, CH2 DATA, . . . at the bottom of the shift register column. Thereby, a serial-to-parallel conversion is achieved with a reduction in the clock rate with the ratio of 8 : 1.
In such a serial-to-parallel converter, however, there exists a problem in that the reduction in the clock frequency is determined by the hardware construction, and because of this, a large area is needed for the hardware when one tries to reduce the clock frequency with a large reduction ratio. It should be noted that the number of bits in the converted parallel output data from the converter corresponds to the number of stages of the shift registers provided in each column. Thus, a large number of shift registers are required to reduce the clock rate of the output parallel data.
On the other hand, in the Josephson processor, input or output of data in response to each high speed clock is not always necessary or desirable, as most of such outputs merely represent the intermediate result of a job and do not represent the desired result of the job. Herein, the job is a set of operations performed to achieve a desired result. It is more usual that the input or output occurs sporadically such that the inputting or outputting of data is made only when a set of complete operations (or a job) defined by program, are completed. The duration of the processing for such operation changes job by job from several clocks to several tens of clocks.
The conversion circuit of FIG. 1 is obviously inappropriate from this view point also, as it lacks the flexibility for responding to the variable duration of the operation carried out in the processor. Further, the circuit of FIG. 1 produces unnecessary, intermediate outputs in response to each of the clocks as already noted. Such unnecessary output data inevitably invites increased complexity in the peripheral circuits that are used to process the output data of the Josephson processor. Associated with the increased complexity, the peripheral circuits suffer from various problems such as decreased yield, increased power consumption, increased signal delay time, and the like.